This invention relates to an apparatus by which elements of a computer can address memory modules, including modules having discontiguous physical addresses, and modules of various sizes, and including the use of interleaving.
In one form of computer architecture, the main memory is formed of multiple memory modules connected at ports of an interconnecting bus, with the possibility of multiple buses, as well. To access a particular data word or byte in memory, it is necessary to provide a physical memory address which includes the address of the bus, the address of the port at which the memory module is connected, and the address of an individual word or byte in a memory module. Conventionally, starting with the lowest memory address, the memory modules are connected at ports of increasingly higher addresses on one bus, and then on buses with increasingly higher addresses, so that there are no unfilled physical memory addresses smaller than the largest occupied physical address in the memory.
Thus, conventionally, the physical addresses of the memory modules are contiguous, increasing in an unbroken sequence from the beginning of memory to the end. This is compatible with logical memory addresses generated by other elements of the computer such as the central processing unit. These logical addresses are likewise contiguous and increase from some starting value to a final value, without any gaps. In such a case, the logical addresses generated by a processing unit or peripheral unit are the same as the physical memory addresses and are used to address words or bytes in the several memory modules.
With respect to the present invention, it was conceived that it would be advantageous if memory modules could be placed at various ports on different interconnecting buses, without being restricted to contiguous physical memory addresses. This is particularly applicable to computer systems wherein the central processing unit, main memory and peripheral units are all connected to ports of the same buses. In the latter type of system, it would be possible, for example, to arrange the elements of a computer in hardware cabinets each of which has a single bus associated with it. A first cabinet might include a processing unit and peripheral devices, so that the bus could not hold a full complement of memory modules. Additional memory modules for the system could be placed in a second cabinet on a second bus, if it were not necessary to maintain contiguous addresses.
The conceived use of a memory with discontiguous physical addresses poses problems. The basic problem is that the software and the processing unit generate contiguous logical addresses, as described above. Moroever, it is desirable to provide a memory operation that allows interleaving, that is, permitting words with adjacent logical addresses to be stored in different memory modules so that access to a second word can be begun before access to a first word is completed. Additionally, there would be an advantage in allowing memory modules of different sizes (capacities) to be installed at the various ports. Presumably, software methods could be devised to achieve some of these objectives; however, they would be unacceptably slow and difficult to manage.
Therefore, it is an object of the invention to permit operation with memory elements having discontiguous physical addresss.
Another object is to provide such operation, along with interleaving capability.
Yet another object is to permit operation with discontiguous physical memory addresses and incorporating memory modules of various capacities.